Guy Barnhart-Magen

November 1, 2019



Academic Publications


With nearly 20 years of experience in the cyber-security industry, Guy held various positions in both corporates and startups.

His current focus is on Security for Machine Learning, System Architecture, and Cryptography, where he provides consulting services in these areas. He is well versed in the Security of machine learning systems, ever since publishing his first paper on using Neural Networks to detect genetic illness.

Most recently, he led Intel’s Predictive Threat Analysis group who focused on the security of machine learning systems and trusted execution environments. At Intel, he defined the global AI security strategy and roadmap. He spoke at dozens of events on the research he and the group have done on Security for AI systems and published several whitepapers on the subject.

Guy is the BSidesTLV chairman and CTF lead, a Public speaker in well known global security events (SAS, t2, 44CON, BSidesLV, and several DefCon villages to name a few), and the recipient of the Cisco “black belt” security ninja honor – Cisco’s highest cybersecurity advocate rank.

He started as a software developer for several security startups and later spent eight years in the IDF. After completing his degrees in Electrical Engineering and Applied Mathematics, he focused on security research, in real-world applications.

He joined NDS (later acquired by Cisco). He led the Anti-Hacking, Cryptography, and Supply Chain Security Groups (~25 people in the US and Israel).

Needing a change, he joined a startup as a CTO. There, he led the team to a successful product, viable architecture, and roadmap.

For blog posts, talks and workshops - please see productsecurity.info

Company Title Duration
Stealth mode Startup CTO and Co-Founder 2019-Now
Melior Security Founder 2019-Now
BSidesTLV BSidesTLV Chairman, CTF Lead 2017-Now
Intel Security Research Manager 2017-2019
Nation-E CTO 2015-2016
Cisco (formerly NDS) Cryptography, Supply Chain Security and Countermeasures Group Manager 2010-2015
HIT B.Sc. in Electrical Engineering (cum laude) and B.Sc. in Applied Mathematics 2006-2010
IDF Executive Officer, Chief Technician 1998-2005



An embodiment of a semiconductor package apparatus may include technology to perform run-time analysis of inputs and outputs of a machine learning model of an inference engine, detect an activity indicative of an attempt to retrieve the machine learning model based on the run-time analysis, and perform one or more preventive actions upon detection of the activity indicative of the attempted model retrieval. Other embodiments are disclosed and claimed.

Publication number: 20190050564

Academic Publications

Active contours: Generalization of the snake mode

Differential Diagnostics of Thalassemia Minor by Artificial Neural Networks Model